Reusing and migrating analog circuit intellectual property (IP) across process nodes poses a significant challenge in modern chip design. Efficient and generalizable circuit performance prediction methods for analog circuits are crucial to achieving this goal. Current data-driven approaches typically rely on manually designed features, which perform poorly on unseen circuit architectures and struggle to model the inherent structural relationships within analog designs. To address these challenges, we propose ACCFormer, a novel topology-aware Transformer framework for predicting performance metrics of analog circuit. Our model combines device parameters with connectivity data to learn topology-aware representations, followed by a performance-oriented cross-attention mechanism where trainable metric queries adaptively focus on the most critical devices for each target parameter. Validated across different process nodes, our model achieves state-of-the-art prediction accuracy and demonstrates strong cross-process adaptability, highlighting its potential to accelerate IP reuse and reduce design cycles.